Limits. Symbol. Parameter. Conditions. −40°C. +25°C. +85°C. Units. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. IL. Quiescent Device. VDD = V. Data sheet acquired from Harris Semiconductor. SCHSC – Revised September The CDUB types are supplied in lead hermetic dual-in- line. Order Number CD C National Semiconductor Corporation . This datasheet has been downloaded from: Datasheets for.
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The other two pairs are more general purpose. However, the second transmission gate, which is now turned ON ensures that the previous logic level at Q is retained through the closed loop with the two-inverter cascade.
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Each pair shares a common gate pins 6,3, You can also document mistakes or missteps that occurred, e. Note each transistor has four cdd4007 That is going to be left as a bonus exercise.
You are encouraged to write down your experience with this lab along with any feedback or suggestions.
Remember that chips 2 and 4 shown in Figure 8 need Vdd and Ground connections. For the complete circuit you will need 4 CD chips. Ids-Vds curves for multiple gate-to-source voltages Vgsfrom which we can observe linear and saturation operation regions.
That is going to be left as a bonus exercise. Such information will datssheet used to improve this and future labs and your experience will help future students.
In each case take a screen-shot. Double transmission gate connections. You should see 3 waveforms similar to the one shown in figure 3.
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Measure the Ids-Vds curves for a multiple Vgs values. Enter search terms or a module, class or function name. During the transparent phase of the latch, i. As a result, any change in the input D is not reflected at the output Q.
D is transmitted to the output Q through the first transmission gate and the two-inverter cascade. Draw a transistor level diagram and a truth table for the circuit. Output of first inverter. The two inverters can be built from a CD by making the following connections: The output of the first inverter will be Vdd and the output of the second inverter will be zero. How does changing R1 and C1 affect the frequency of the output?
Two copies with opposite phase clocks will then make a master-slave D Flip Flop. We will now combine the double transmission gate built in the previous exercise with inverter chain of the first exercise to build a D-latch as shown in Figure 7.
Attach screen shots for working frequencies, and for too high frequencies such that transitions between 0 and VDD are not complete. A low budget way to avoid static discharge is to ground yourself before touching an IC. Therefore, this circuit is an oscillator. Adjust frequency until you can see a clear rise and fall of the output signal.
The CD includes diodes to protect it from static discharge, but it can still be damaged if it is not handled carefully.
Fairchild Semiconductor – datasheet pdf
It should look as shown below in Figure 5. Connect pin 9, which serves as D input of the latch ce4007 DIO0. What to do in lab report Show 3 screen shots of inverter outputs. Proceed as shown in Figure 6.
Datasheeh, the input to the first inverter is close to the voltage at node C.
Capture a screen shot. Remove the capacitor from the previous step.
Observe the DIO8 pin. There are 6 parts and a bonus. Thank cd datasheet for keeping our lab clean and organized. A steady high should appear. There are many advantages of CMOS, with the biggest being zero standby power consumption, at least ideally.